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12th IEEE Santa Clara Valley Industry Spotlight – Fast Lanes for Expedited Execution at 10 Terabits

TOPIC: FLEET — Fast Lanes for Expedited Execution at 10 Terabits

SPEAKER:  Fred Douglis, Chief Scientist, Perspecta Labs, Basking Ridge, NJ

DATE: Tuesday, May 25th 2021, 6pm PT (Pacific Timezone)
REGISTER: https://forms.gle/oEyq88LTKDoRi1XS8
SOCIAL MEDIA: www.linkedin.com/in/freddouglis; twitter.com/FredDouglis
WATCH PAST TALKS: https://youtube.com/playlist?list=PLb8j28CYROlwx1sgQmFUw7uMD1GCXbpfS
WEBSITE: https://site.ieee.org/scv/scv-corporate-liaison-program/
SPONSORS: IEEE SCV Section, IEEE Computer Society  SCV Chapter; IEEE Industry Engagement


The DARPA FastNICs program targets orders of magnitude improvement in applications such as deep learning training by making radical improvements to network performance: while raw bandwidth has grown dramatically, the fundamental roadblock to application performance has been in delivering  that data to the application. FLEET provides a primarily off-the-shelf solution with high-end servers and shared computational and storage resources connected via PCIe over a reconfigurable MEMS optical switch; it uses custom Optical NICs to allow arbitrary topologies that can be configured before or even during execution to take advantage of shared resources and to flow data between components. FLEET’s software is derived from Stanford Legion, which we are modifying to use the FLEET hardware and to plan application execution for these dynamic network topologies.


Dr. Fred Douglis is a Chief Research Scientist at Perspecta Labs since January 2018, where he works on applied research in the areas of high-performance computing, edge computing, blockchain, and others. He was previously with companies including Matsushita, AT&T, IBM, and (Dell) EMC. His other research interests have included storage, distributed systems, web tools and performance, and mobile computing. He holds a Ph.D. in computer science from U.C. Berkeley. Douglis is a member of the IEEE Computer Society Board of Governors and a fellow of the IEEE.


Consider submitting a paper to SC’21 Workshop: Programming Environments for Heterogeneous Computing (PEHC). Co-chairs: Rosa M. Badia, Maya Gokhale, Torsten Hoefler, Wen-mei Hwu, Hironori Kasahara, and Dejan Milojicic. Submission deadlines are June 16 (abstract) and June 23 (full paper). Submissions are 5 pages long on innovative work addressing heterogeneity. Submission page. Read more.

Best Regards,
Dejan Milojicic, IEEE Santa Clara Valley Section: Corporate Liaison Program Chair, Computer Society Chapter Chair.

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