CALL FOR PAPERS
28th International Conference on Microelectronic Test Structures
March 23-26, 2015, DoubleTree Phoenix/Tempe Hotel, Phoenix, Arizona USA
The 28th International Conference on Microelectronic Test Structures (ICMTS) will be held in Phoenix, Arizona, USA, bringing together designers and users of test structures to discuss recent developments and future directions. The conference will be held March 24-26, 2015, preceded by a one-day Tutorial Short Course on Microelectronic Test Structures on March 23. There will be an equipment exhibition relating to test structures and measurements. Original papers are solicited presenting new developments in test structures, as well as their implementation, measurement, and application, related to semiconductors, nanotechnology, and MEMS. A Best Paper award will be presented by the Technical Program Committee. The conference is sponsored by the IEEE Electron Devices Society and all published papers will be posted to IEEE Xplore®.
Topics of relevance (see below for additional information) to ICMTS include, but are not limited to:
Material and Process Characterization
Test structure design methods
Replicated Feature Metrology
Manufacturing of Integrated Circuits and MEMS
Reliability and Product Failure Analysis
Nanotechnology, Displays, and Emerging Devices
(BIO-)MEMS, (BIO-)Sensors, and Actuators
Device and Circuit Modeling, Parameter Extraction
Technology R&D, Integration, and DFM
Test Circuits
Yield Enhancement, and Production Process Control
Test Structure Measurement Utilization Strategy
Matching and Variability Test Structures
Authors are asked to submit an abstract of up to four pages in PDF format (font-embedded). The first page must consist of a title, a 50-words summary, author name(s), the full address, fax number, and e-mail address of the lead author, and author preference for oral or poster session presentation, if any. The body of the abstract should be three pages or less consisting of one page of text (800 to 1000 words) and up to two pages containing major figures and tables. Please visit the ICMTS 2015 official web site icmts2015.pdf.com for further information and paper submission. You may care to join the ICMTS group at www.linkedin.com.
The selection process will be based on the technical merit and will be highly weighted in favor of papers that have a high test structure content, include measured data and analysis, together with illustrations of the test structures involved. The submission deadline is October 17, 2014. Notice of paper acceptance, with instructions for manuscript preparation for the conference proceedings, will be sent to the authors of the papers selected for presentation by early December, 2014. The deadline for submission of the final paper will be January 20, 2015.
Details of the venue, hotel, registration, etc. will be posted at icmts2015.pdf.com as they are finalized.
For further technical information, please contact the technical chair: Colin McAndrew, Freescale Semiconductor, Inc., Colin.McAndrew@freescale.com
General Chair:
Larg Weiland
PDF Solutions
larg.weiland@pdf.com
Technical Chair:
Colin McAndrew
Freescale Semiconductor, Inc.
Colin.McAndrew@freescale.com
Tutorial Chair:
Brad Smith
Freescale Semiconductor, Inc.
Brad.Smith@Freescale.com
Local Arrangements:
Colin McAndrew
Freescale Semiconductor, Inc
Colin.McAndrew@freescale.com
Equipment Exhibition:
Bill Verzi
Agilent/Keysight Technologies
bill_verzi@agilent.com
TOPICS OF RELEVANCE:
Test structure design methods: Flows for automated test structure design, generation, and verification; design-for-analysis, parameterized design, layout issues (grid, hierarchy, misalignment), switched arrays.
Replicated Feature Metrology: Level-to-level registration, overlay, CD uniformity and control, non-electrical characterization techniques, mask and reticle process control.
Manufacturing of Integrated Circuits and MEMS: Evaluation of individual and groups of integrated circuit, device, and MEMS process steps and elements: transistors, diodes, mechanical structures, device isolation, memory cells, and interconnect. Assessment of MMICs and RF components and products. Evaluation and optimization of standard cell macros and other circuits.
Reliability and Product Failure Analysis: Test structures for quality assurance, transistor, thin film, dielectric, and interconnect reliability, thermal monitoring and analysis, accelerated wafer level tests, wafer level burn-in, failure identification, reliability prediction.
Nanotechnology, Displays, and Emerging Devices: Test structures and methods to evaluate nanotechnology (materials and devices), displays, optoelectronic materials and devices, novel memories, and related materials.
(BIO-)MEMS, (BIO-)Sensors, and Actuators: Test structures for MEMS and micromachining including physical/chemical/optical/bio sensors, photonic devices, amorphous silicon films and devices.
Device and Circuit Modeling, Parameter Extraction: Model parameter extraction, RF device modeling, de-embedding, pulsed measurements, DC and high frequency measurement techniques and applications.
Technology R&D, Integration, and DFM: Test structures for FEOL or BEOL evaluation, design rule determination, process uniformity and worst-case analysis, test structures to assess integration and new technologies, switched array test chips/devices for large scale evaluations and reduced pad count.
Test Circuits: Novel on-wafer circuits for characterization of manufacturing technologies, variability, yield, and performance. Circuits to simplify probing, improve measurement robustness, and reduce pad count.
Yield Enhancement, and Production Process Control: Yield enhancement structures and methods, critical area calculation, defect estimation structures and methods, yield modeling, evaluation of design-manufacturing interactions, place and route methodology, and statistical process control. Large-scale, many-component test arrays and multiplexing techniques for technology assessment.
Test Structure Measurement Utilization Strategy: Test equipment, probing and programmable testing for process diagnostics, optimizing test throughput, database and data analysis methods, statistical data analysis, expert systems and related techniques, including capacitance, voltage, current, resistance, optical, and thermal measurements.
Matching and Variability Test Structures: Matching and variability of components (transistors, resistors, capacitors, inductors) and layout for circuit applications and their evaluation. Characterization of identically designed components. Modeling of matching and variability.
