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Silicon Valley Area Chapter

(SCV, SF, OEB)

Slides and Video Links from Past Meetings

If you missed one of our technical meetings, we invite you to download the slides, or view the archived video.

Click on an event of interest to access a link to slides or video. 

You can also use the Search box (above) to scan for topics or speakers.
Design and Analysis of Chiplet Interfaces for Heterogeneous Systems (Wendem Beyene) — mixed technologies/nodes, parallel interconnects, power domains, supply noise, timing jitter …
Scheduled
(on the Internet)
Packaging of Electronics for Medical, Health and Wearables Applications — (Mark Poliks) heterogeneous integration, advance packaging, new materials, assembly technologies, forecasts …
Scheduled
Design for Reliability and Accelerated Testing in Electronics and Photonics Packaging Engineering — (Ephraim Suhir) improved reliability, critical applications, product lifetime, DfR, HALT …
Scheduled
Integrated Photonics for Heterogeneous Integration — (Bill Bottoms) design, analysis, current capabilities, challenges …
Scheduled
On the Internet
Co-Design for Heterogeneous Integration — (José Schutt-Ainé) electrical, thermal, mechanical, chip-package-board, design flow, new tools …
Scheduled
Modeling and Simulation for Heterogeneous Integration — (Chris Bailey) enabling technologies, tools, chip-package-board-system domains, challenges …
Scheduled
Thermal Management Challenges and Opportunities for Heterogeneous Packages — (Madhu Iyengar, Mehdi Asheghi) cooling requirements, advanced concepts, thermal challenges, active research areas, HI Roadmap …
Scheduled
Heterogeneous Integration Roadmap: Interconnects for 2D and 3D Architectures — (Ravi Mahajan) definitions, evolution, key metrics, bandwidth, power delivery, signaling …
Scheduled
On the Internet
The Rise of Chiplets: The ODSA Project — (Bapi Vinnakota) end of Moore’s Law, rise of chiplets, ODSA D2D Interface, abstraction layer, reuse …
Scheduled
SEMI World Hdqtrs, Milpitas
Chiplets on the Rise: DARPA’s CHIPS Program (David Kehlet) — early days, DARPA, standardization, plug-and-play, open-source, new ecosystem …
Scheduled
SEMI World Hdqtrs, Milpitas
Virtuous Cycle of AI: System-level Challenges — (Pradeep Dubey) AI transformation, data-intensive, impacts, performance challenges, application opportunities …
Scheduled
SEMI World Hdqtrs, Milpitas
System in Package (SiP) for Miniaturized Electronics Modules: An Update — miniaturized modules, technology landscape, requirements, solutions, flexible electronics …
Scheduled
SEMI World Hdqtrs, Milpitas
Visualizing the Packaging Roadmap — ITRS, Moore’s Law, innovation, roadmaps, packaging issues, hi-performance computing, solutions …
Scheduled
SEMI World Hdqtrs, Milpitas
FPGA Heterogeneous Packaging Applications: Trends and Challenges — HPC, networking, cloud services, automotive, logic/memory integration, thermal, evolution …
Scheduled
TI Conference Center, Santa Clara
The Road Ahead: Outlook for the Electronics Packaging Industry — projections for AI, autonomous vehicles, crypto, OSATs, foundries, outlook …
Scheduled
TI Conference Center, Santa Clara
2D to 3D Package Architectures: Back to the Future — scaling, heterogeneous integration, impact on power, performance, latency, nomenclature for package architectures, current metrics, projections …
Scheduled
TI Conference Center, Santa Clara
Trends and Transitions in Semiconductor Packaging — business models, supply chain, technology requirements, forecast for 2018 and 2019 …
Scheduled
TI Conference Center, Santa Clara
Heterogeneous Packaging Integration for Electronics Systems — mobile products, system-on-chip, dissimilar chips, performance, cost, SiP, TSV, interposers, forecast …
Scheduled
TI Conference Center, Santa Clara
How to Peel Ultra-Thin Dies from Wafer Tape — bending stress, die strength, peel force, die structures, wafer processing steps, TSVs, pickup methods, experimental verification …
Scheduled
TI Conference Center, Santa Clara
Comparison of Die Singulation Techniques — die thinning, stealth laser, laser abrasion, plasma etch, rotary blade, results …
Scheduled
TI Conference Center, Santa Clara
Ten Years of Robustness Validation Applied to Power Electronics Components — European car makers, physics of failure, “test to fail”, end-of-life testing, thick wire bonds, planar interconnects …
Scheduled
TI Conference Center, Santa Clara
Developing Technology for Autonomous Vehicles and Electric Cars: The Next Platform — half-day Workshop: automotive environment, materials, packaging, devices for 5G, LiDAR, RADAR …
Scheduled
TI Conference Center, Santa Clara
Intel Silicon Photonics: From Research to Product — optical, SiPh, standard silicon processing, performance, low-cost, optical100G transceiver …
Scheduled
TI Conference Center, Santa Clara
Advances in Low Cost/High Reliability Lead-Free Solder Materials — solder’s role, compositions, properties, Ag content, optimum cost/reliability, failure modes …
Scheduled
TI Conference Center, Santa Clara
Roll-to-roll Manufacturing in Electronics: Making it Work — charge-array, deposition, registration, evolution, flip-chip and TFTs …
Scheduled
TI Conference Center, Santa Clara
Wafer-Level Process Formation of a Polymer-Isolated Chip-Scale Package — yield loss, leakage, sidewall insulation, protection, reliability results …
Scheduled
TI Conference Center, Santa Clara
Advances in Plasma Nano-coating — properties, density, pinhole-free, thicknesses, corrosion resistant, environmentally benign …
Scheduled
TI Conference Center, Santa Clara
Wafer Level Encapsulation – Challenges And Solutions on an Alternative Format for Discrete Packaging — wafer level, molding, encapsulant, warpage control, lower cost …
Scheduled
TI Conference Center, Santa Clara
Embedding and Miniaturization in Electronics Packaging — market needs, form-factors. wearables, cameras, consumer electronics, power converters …
Scheduled
TI Conference Center, Santa Clara
Package Requirements for High-Speed Systems — SiP solution, enabling technologies, applications, packaging, market segments …
Scheduled
TI Conference Center, Santa Clara
Recent Advances and Trends in Semiconductor Packaging – fan-out wafer/panel-level, 2.5D/3D, embedded, MEMS/IC integration …
Scheduled
TI Conference Center, Santa Clara
A Flexible Manufacturing Platform for High-Volume TCB and High Density FOWLP — TC bonding, drivers, accuracy, platform, advanced processes …
Scheduled
TI Conference Center, Santa Clara
 
Thermal Engineering Associates
Submitted by past chair Bernie Siegal, of Thermal Engineering Associates. These flipchip dies help provide data on heat management.
ASE Photo
Wirebonders at ASE. Courtesy of ASE
StatsChipPac photo
Courtesy of StatsChippac.
Zuken photo
Courtesy of Zuken. Interconnection Intricacies inside the design of a multichip package

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IEEE Santa Clara Valley Chapter, EPS, Serving Silicon Valley and the SF Bay Area. © Copyright 2020 IEEE – All rights reserved. Use of this Web site signifies your agreement to the IEEE Terms and Conditions
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Home  |  Contact IEEE Santa Clara Vally Chapter, EPS  |  Accessibility  |  Privacy & Opting Out of Cookies  |  Nondiscrimination Policy

IEEE Santa Clara Valley Chapter, EPS
Serving Silicon Valley and the SF Bay Area
© Copyright 2020 IEEE – All rights reserved. Use of this Web site signifies your agreement to the IEEE Terms and Conditions.
A not-for-profit organization, IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity.