Silicon Valley Area Chapter


Visualizing the Packaging Roadmap 🗓 🗺

-- ITRS, Moore's Law, innovation, roadmaps, packaging issues, hi-performance computing, solutions ...

Speaker: Ivor Barber, Corporate VP for Packaging, AMD
Presentation Slides: “Visualizing the Packaging Roadmap” (1.7 MB PDF)
Meeting Date: Wednesday, March 13, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE/MEPTEC members students, unemployed; $10 non-members

Location: SEMI World Hdqtrs, 673 South Milpitas Blvd, Milpitas
Summary: With the end of Moore’s Law as an economic driver at 28nm, and publication of the final edition of the ITRS in July 2016, we find packaging is now on the center stage of semiconductor innovation — but what roadmap do we follow? This presentation will discuss prior roadmaps and how the packaging industry is responding with a product-based integrated solution roadmap. The presenter will discuss the goals of Heterogeneous Integration for High Performance Computing Applications and the packaging solutions this will drive.

Bio: Ivor Barber is currently Corporate VP for Packaging at AMD with responsibility for all Packaging activity from Design through High Volume Manufacturing. With over 35 years experience in the Semiconductor Industry, Ivor has held various Engineering and Management positions in Assembly, Package Characterization and Package Design at National Semiconductor, Fairchild Semiconductor, VLSI Technology, LSI Corporation and Xilinx. Ivor graduated from Napier University in Edinburgh, Scotland with a Bachelors degree in Technology and holds 15 US patents related to packaging.

Scheduled meetings slides
SEMI World Hdqtrs, Milpitas Map