Silicon Valley Area Chapter


FPGA Heterogeneous Packaging Applications: Trends and Challenges 🗓 🗺

-- HPC, networking, cloud services, automotive, logic/memory integration, thermal, evolution ...

Co-sponsored by the Solid State Circuits Chapter
Speaker: Suresh Ramalingam, PhD., Fellow, Manager Advanced Packaging Interconnect Technology Development, Xilinx
Presentation Slides: “FPGA Heterogeneous Packaging Applications: Trends and Challenges” (1.6 MB PDF)
Meeting Date: Wednesday, November 14, 2018
Time: 11:30 AM Registration (and pizza/water); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara

Summary: Deep learning and artificial intelligence are at the heart of today’s technological innovations. Driven by advanced applications in HPC (High Performance Computing), Networking, Cloud Services and Automotive, demand for high bandwidth, lower latency and lower system power solutions have gained a lot of interest and momentum. As HPC designs move to several TB/sec and Telecom pushes to 400G/800G systems, bottlenecks in lower-latency memory bandwidth require HBM (High Bandwidth DRAM Memory) integration.
Advanced heterogeneous packaging based on 2.5D CoWoS®/3D/Fan-out InFO or other platforms are required to address various Logic and memory integration. The inexorable push towards higher performance “system in a package” solutions coupled with silicon technology scaling and cost challenges is expected to stretch the heterogeneous packaging boundaries much further. Thermal solutions are also becoming an active area of focus as the power levels are expected to push beyond 500W.
In this presentation we will examine FPGA Heterogeneous Packaging evolution working together with TSMC, industry trends and challenges. Since a system-level perspective is very important, we will touch upon some of the mechanical and thermal challenges and trends, and interplay with the package.

Bio: Dr. Suresh Ramalingam graduated in 1994 with a Ph.D. in Chemical Engineering from the Massachusetts Institute of Technology. He holds 24 US Patents, the 2013 SEMI Award, the Ross Freeman Award for Technical Innovation, ECTC 2011’s Conference Best Paper Award, and IMAPS 2013 and 2014 Conference Best Paper Awards for 2.5D/3D. He started his career at Intel developing Organic Flip Chip Technology for microprocessors which was implemented on Pentium I (Intel’s first flip chip product for laptops) in 1997. As one of the co-founders and Director of Packaging Materials at Scion Photonics, he helped develop DWDM modules used by major communication companies. JDS Uniphase acquired Scion Photonics in 2002. As a Xilinx Fellow, he currently manages Advanced Packaging Interconnect Technology Development including TSV/3D for Xilinx FPGA products.

Scheduled meetings slides
TI Conference Center, Santa Clara Map