Silicon Valley Area Chapter


2D to 3D Package Architectures: Back to the Future 🗓 🗺

-- scaling, heterogeneous integration, impact on power, performance, latency, nomenclature for package architectures, current metrics, projections ...

Speaker: Dr. Raja Swaminathan, Package Architect
Presentation Slides: “2D to 3D Package Architectures: Back to the Future” (1.5 MB PDF)
Meeting Date: Thursday, May 3, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: (URL)
Summary: Moore’s Law Scaling has driven electronics industry growth and new package architectures (including 3D architectures and architectures currently defined as 2.1D, 2.3D or 2.5D architectures) are projected to be major enablers to maintain the pace of Moore’s law scaling and enable heterogeneous integration. Historically, packaging has scaled sufficiently to act as a space and electrical transformer to enable transistor/silicon scaling, and innovations in packaging were focused on minimizing impact to the power, performance and latency of silicon. With an increasing drive for heterogeneous integration, packaging is being increasingly challenged to deliver power-efficient, high bandwidth on/off package low power links and meet diverse functionality ranging from high performance servers to flexible, wearable electronics. This talk will introduce a new IEEE standardized industry nomenclature on package architectures covering and clearly demarcating both 2D and 3D constructions, as well as highlight the key metrics driving the evolution of these architectures, their current values (based on the state of the art) and projections for the next 5-10 years. This is expected to drive focus and direction to industry, academia and government on critical technology trends and motivations for research needed to meet next generation requirements in the 2D-3D architecture space.

Bio: Dr. Raja Swaminathan is an IEEE senior member and was a package architect at Intel for next generation server, client and mobile products. His expertise is on delivering integrated HVM-friendly package architectures with optimized electrical, mechanical, and thermal solutions. He is an IEEE, ITRS and iNEMI Roadmap author on packaging and design, and recently drove industry convergence of 2D and 3D architecture nomenclatures and design, process and electrical metrics. He has also served on IEEE micro-electronics and magnetics technical committees and has been key note speaker in electronics conferences. He has 26 patents and 25 peer-reviewed publications and holds a Ph.D. in Materials Science and Engineering from Carnegie Mellon University.

Scheduled meetings slides
TI Conference Center, Santa Clara Map