Silicon Valley Area Chapter


3D Packaging for Superconducting Qubits 🗓

(RN Das) -- more chips, microbump-based assembly, three-tier stacks, alignment accuracy, co-planarity ...

Speaker: Rabindra N. Das, MTS, Quantum Information and Integrated Nanosystems Group, MIT Lincoln Laboratory
Meeting Date: Thursday, May 13, 2021
Time: Checkin via WebEx at 11:50 AM; Presentation at 12:00 noon (PDT)
Cost: none
Summary: Superconducting qubits are a leading candidate for constructing a large-scale quantum processor due to their lithographic scalability and relatively long coherence times. 3D qubit packaging, enabling the integration of more chips with greater functionality, higher I/O counts, and smaller pad pitches –- while maintaining qubit coherence –- is critical for scalable computing architecture. In this talk, I will present a microbump-based assembly approach to produce three-tier stacks with a qubit chip on the top, superconducting multi-chip-module (SMCM) on the bottom, and an interposer chip with superconducting through-silicon vias (TSVs) in the middle. I will discuss our work developing a double bump-bonding process to create the qubit-interposer-SMCM stack, focusing on electrical characterization, alignment accuracy, spacing and co-planarity.
This research was funded by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), the Defense Advanced Research Projects Agency (DARPA), and by the Assistant Secretary of Defense for Research & Engineering under Air Force Contract No. FA8702-15-D-0001.

Bio: Rabindra N. Das is a Member of the Technical Staff in the Quantum Information and Integrated Nanosystems Group, MIT Lincoln Laboratory, Lexington, MA. Prior to MIT, he was a Principal Engineer at Endicott Interconnect Technologies (formerly IBM Endicott). Dr. Das has 18 years of experience in microelectronics packaging development for applications ranging from HPC to medical to quantum electronics. He holds 48 patents and more than 100 publications.

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