Silicon Valley Area Chapter

(SCV, SF, OEB)

Bonding Technology for the Next Generation Integration Schemes 🗓

(Jurgen Burggraf) -- die shrink, yield, heterogeneous chips, interconnect challenges, wafer bonding ...

Speaker: Jürgen Burggraf, Process Technology Manager, EV Group (Austria)
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Meeting Date: Thursday, June 10, 2021
Time: Checkin via WebEx at 7:50 AM; Presentation at 8:00 AM (PDT)
Cost: none
Reservations: eps2106b.eventbrite.com
Summary: As Moore’s law is reaching its limits, advanced packaging has taken leadership to drive the race for IC performance. On the one hand, the die size is constantly reduced, so heterogeneous integration with high interconnect density becomes critical, especially for small package dimensions. For example, this is the case in IoT or mobile applications. Here, heterogeneous integration leads to an overall increased yield, mainly as smaller dies generally can be produced with higher yield. At the same time and most importantly, memory, processors, sensors and other dies from different sources can be combined using heterogeneous integration. The main drivers for heterogeneous integration using advanced packaging are the strong demand for low-power multichip mobile components, with constantly reduced lateral form factors. Various bonding processes are becoming essential to fulfill and enable new integration needs of new integration flows. Wafer bonding technologies such as dielectric-dielectric fusion, dielectric-metal hybrid bonding, collective die-to-wafer bonding, and oxide-free fusion wafer bonding will be presented.

Bio: Jürgen Burggraf started at EV Group (EVG) in 2007 as a Process Technology Engineer for wafer bonding applications. Currently Jürgen is the Process Technology Manager for wafer bonding and he is responsible for EVG’s worldwide process development for wafer bonding, such as temporary wafer bonding/debonding and permanent bonding. He holds an engineering degree in Bionic & Sensor Technology and a diploma degree in industrial engineering.

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