Silicon Valley Area Chapter


Wafer Level Encapsulation – Challenges And Solutions on an Alternative Format for Discrete Packaging 🗓 🗺

— wafer level, molding, encapsulant, warpage control, lower cost ...

Speaker: Eric Kuah, VP of Technology, ASM
Meeting Date: Wednesday, October 19, 2016
Presentation Slides: “Wafer Level Encapsulation – Challenges And Solutions on an Alternative Format for Discrete Packaging” (5 MB PDF)
Time: 5:45 PM Registration (and sandwiches/drinks); 6:30 PM Presentation
Presentation-only: 6:30 PM (come at 6:15)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara

Summary: The discrete package production is a very sizeable market, offering many different packages for a variety of applications such as ESD protection, MOSFETS among others. These packages act as a function for voltage/current protection, electrical/electronic filtering, and power efficiency improvement. The current packaging and assembly methodologies use leadframe to produce packages such as DSN, DFN, SOD and SOT. The advent of producing these packages on either the wafer or panel level format has arrived. In our recent packaging and assembly work we found that producing discrete package using wafer level format is feasible from the perspective of cost of production and technology . From the viewpoint of cost production, a significant portion of the manufacturing process can be eliminated, for instance interconnected technologies using wire bonding. This will translate into a reduction in cost of production and an increased throughput. In the aspect of technology, power efficiency can be further improved. Take for an example, a DSN. A real estate of 30mm2 with a power density of 60 mW/mm2 can be reduced to a smaller real estate of 1.1mm2 with a power density of 1000 mW/mm2. The focus of our presentation is to share our experience in producing such package, and in particular encapsulation. We will discuss the challenges and solutions that a packaging/equipment engineer will face during the molding process of these discrete packages at a wafer level. Technical solutions to be discussed are material handling, encapsulation tool design, encapsulant selection, warpage control, voiding, and moldability solutions. The package format of our work is carried out on an 8” silicon wafer that allows one to produce it as either a 5S (five-sided package) or 6S (six-sided package) discrete package.

Bio: Eric Kuah has been the Vice President of Technology at the Encapsulation Solutions Group of ASM since 1993. He received his BSME (summa cum laude) and MSME from Ohio University (Athens) in 1985 and 1987, respectively, and a second Masters in Theoretical and Applied Mechanics from the University of Illinois (Urbana-Champaign) in 1993. In 2000, Eric earned his MBA in Management of Technology from Nanyang Technological University, and was awarded the Singapore Institute of Engineer Gold medal.

Scheduled meetings slides
TI Conference Center, Santa Clara Map