Silicon Valley Area Chapter


Recent Advances and Trends in Semiconductor Packaging 🗓 🗺

- fan-out wafer/panel-level, 2.5D/3D, embedded, MEMS/IC integration ...

– fan-out wafer/panel-level, 2.5D/3D, embedded, MEMS/IC integration …
Speaker: Dr. John H. Lau, Sr. Technical Advisor, ASM
Slides: Download here (3 MB PDF)
Date: Tuesday, April 12, 2016
Time: 11:300 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Summary: Recent advances in, for example, fan-out wafer/panel level packaging (TSMC’s InFO-WLP and IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers), embedded 3D hybrid integration (of VCSEL, driver, serializer, polymer waveguide, etc.), 3D CIS/IC integration, and 3D MEMS/IC integration are examined and their new trends will be discussed in this lecture. The patents impacting the semiconductor packaging the most (so far) will be mentioned first and the patent issues of fan-out wafer/panel-level will be discussed and some recommendations will be made.

Bio: John H. Lau has been a Sr. Technical Advisor of ASM since July 2014. Prior to that, he was a Senior Scientist/MTS at Hewlett-Packard/Agilent for more than 25 years. With more than 38 years of R&D and manufacturing experience, he has published more than 440 peer-reviewed papers, 30 issued and pending patents, and 20 textbooks on, e.g., Reliability of RoHS compliant 2D and 3D IC Interconnects (2011), TSV for 3D Integration (2013), and 3D IC Integration and Packaging (2015). He is an IEEE Fellow and ASME Fellow.

Scheduled meetings slides
TI Conference Center, Santa Clara Map