Silicon Valley Area Chapter


Co-Design for Heterogeneous Integration 🗓

-- (José Schutt-Ainé) electrical, thermal, mechanical, chip-package-board, design flow, new tools ...

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Speakers: Prof. José Schutt-Ainé, UI-UC, and Prof. Rohit Sharma, Indian Institute of Technology Ropar
Webinar Date: Thursday, July 23, 2020
Time: 8:00 AM (PDT)
Cost: none
Location: On the Internet
Summary: This talk focuses on current state-of-the-art, challenges and potential solutions for Co-Design. Electrical, thermal, and mechanical interactions across the chip-package-board domains can no longer be ignored. New modelling and simulation tools must accurately predict the physical (e.g. electro-thermal, thermo-mechanical, etc) coupling between multiple semiconductor components and the package/system that contains them. The Co-Design Chapter of the Heterogenous Integration Roadmap explores how design and analysis practices need to be defined in the context of heterogeneous integration. It addresses the traditional chip-package-board design flow as well as current capabilities and future challenges. The vision is to create an environment where design closure is achieved with a minimum number of iterations meeting all requirements for performance and cost. This environment must leverage from currently available technologies, namely computing power, algorithms and artificial intelligence.
Download Chapter 13, Co-Design for Heterogeneous Integration for pre-Webinar study.
José Schutt-Ainé Bio: José Schutt-Ainé received the B.S. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1981, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign (UIUC), Urbana, in 1984 and 1988, respectively. In 1989, he joined the Electrical and Computer Engineering Department as a member of the Electromagnetics and Coordinated Science Laboratories, where he is currently involved in research on signal integrity for high-speed digital and high-frequency applications. He is a consultant for several corporations. His current research interests include the study of signal integrity and the generation of computer-aided design tools for high-speed digital systems. He is an IEEE Fellow and served as Co-Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology (T-CPMT) from 2007 to 2018.
Rohit Sharma Bio: Rohit Sharma received the B.E. degree in electronics and telecommunication engineering from North Maharashtra University, India, in 2000, the M. Tech. degree in systems engineering from Dayalbagh Educational Institutes, India, in 2003 and the Ph.D. degree in electronics and communication engineering from Jaypee University of Information Technology, India, in 2009. He worked as a Post-Doctoral Fellow at the Design Automation Lab at Seoul National University, Seoul, Korea from Jan 2010 to Dec 2010. He was a Post-Doctoral Fellow at the Interconnect Focus Centre at Georgia Institute of Technology, Atlanta, USA from Jan 2011 to Jun 2012. Dr. Sharma joined the department of electrical engineering at the Indian Institute of Technology Ropar in 2012, where he is currently an Associate Professor. All along his tenure at IIT Ropar, he has initiated activities in the area of Electronic Packaging. His current research interests include design of high-speed chip-chip and on-chip interconnects, Graphene based nanoelectronic devices and interconnects, Signal and Thermal integrity in high-speed interconnects and 3D ICs/packages and application of Machine Learning in advanced packaging and systems. He is also the coordinator of the Indo-Taiwan Joint Research Centre on Artificial Intelligence and Machine Learning at IIT Ropar. He is an Associate Editor of the IEEE Transactions on Components, Packaging and Manufacturing Technology and a Program Committee member in IEEE EPEPS and IEEE EDAPS. He has been the General Co-Chair of the IEEE EDAPS in 2018. He is the Co-Chair of the IEEE EPS Technical Committee on Electrical Design, Modeling, and Simulation and is a Senior Member of the IEEE.

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