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Silicon Valley Area Chapter

(SCV, SF, OEB)

Learn about advances in device packaging designs, methods, materials, processes and reliability

Chip_effects_glow-shadow

Learn about advances in device packaging designs, methods, materials, processes and reliability

Learn about advances in device packaging designs, methods, materials, processes and reliability

Upcoming Meetings and Webinars

High Performance and Reliable Aerosol Jet Printed 3D Interconnects for Bare Die and Components (Bryan Germann) — flex, wearable, power, signal, bandwidth, performance, implementation, production, examples …
Scheduled ical Google outlook
(on the Internet)
Design and Analysis of Chiplet Interfaces for Heterogeneous Systems (Wendem Beyene) — mixed technologies/nodes, parallel interconnects, power domains, supply noise, timing jitter …
Scheduled ical Google outlook
(on the Internet)
Fourth Annual Symposium on Heterogeneous Integration — future packaging for mobile, HPC, automotive, 5G, health, Chiplets, work on 2021 Roadmap …
Scheduled ical Google outlook
(on the Internet)
Working Group Meetings: 2021 IEEE Heterogeneous Integration Roadmap
from to
Scheduled ical Google outlook
(on the Internet)
Heterogeneous Integration of Surface Ion Trap, Silicon Photonics and 3D-TSV for Quantum Computing (CS Tan) — CMOS technology, optical addressing, parasitics, glass substrate, ground plane, improved performance …
Scheduled ical Google outlook
(on the Internet)
Additively-Printed Multilayer Flexible Substrates with Z-axis Interconnects (Pradeep Lall) — aerosol-jet, inkjet, direct-write, screen print, multi-layer, process factors, performance …
Scheduled ical Google outlook
(on the Internet)
Package Technology, Design, and Methodology Challenges and Solutions for High Bandwidth Electronic Systems (Kemal Aygun) — interchip, IO bandwidth, fan-out, 2.5D packaging, design, analysis, validation …
Scheduled ical Google outlook
(on the Internet)
Dr. Ivor Barber of AMD presenting at one of our luncheon talks.

Dr. Ivor Barber of AMD presenting at one of our luncheon talks.

Upcoming Conferences and Workshops

Fourth Annual Symposium on Heterogeneous Integration — future packaging for mobile, HPC, automotive, 5G, health, Chiplets, work on 2021 Roadmap …
Scheduled ical Google outlook
(on the Internet)
Working Group Meetings: 2021 IEEE Heterogeneous Integration Roadmap
from to
Scheduled ical Google outlook
(on the Internet)

Slides and Webinars from Past Meetings

Packaging of Electronics for Medical, Health and Wearables Applications -- (Mark Poliks) heterogeneous integration, advance packaging, new materials, assembly technologies, forecasts ...
Scheduled
Design for Reliability and Accelerated Testing in Electronics and Photonics Packaging Engineering -- (Ephraim Suhir) improved reliability, critical applications, product lifetime, DfR, HALT ...
Scheduled
Integrated Photonics for Heterogeneous Integration -- (Bill Bottoms) design, analysis, current capabilities, challenges ...
Scheduled
On the Internet
Co-Design for Heterogeneous Integration -- (José Schutt-Ainé) electrical, thermal, mechanical, chip-package-board, design flow, new tools ...
Scheduled
Modeling and Simulation for Heterogeneous Integration -- (Chris Bailey) enabling technologies, tools, chip-package-board-system domains, challenges ...
Scheduled

Additional Slides and Videos

Join our E-Mail List

An advanced pre-production package, held by UC-Davis graduate A. Nguyen, a packaging engineer

Message from Chapter Chair, Annette Teng

Annette Teng
Annette Teng
    Welcome, and thank you for visiting our IEEE-EPS-Silicon Valley Chapter website. Whether you are IEEE member or casual onlooker, we hope you can enjoy our website and find us of value to you.    Since our inception over 50 years ago, EPS-SCV has provided a valuable forum for those who are interested in learning and exchanging knowledge relating to electronic packaging design, assembly, test, thermal and stress management. Our chapter is a facilitator for sharing knowledge and networking with others through activities such as lunch talks, symposiums and factory visits. We normally hold a monthly lunch seminar at SEMI Headquarters in Milpitas. However, since the shelter-in-place came into effect, we have organized a series of EPS webinars in the area of device package heterogeneous integration and the HI Roadmap. Slides and videos from past seminars can be downloaded/viewed from this webpage. Membership is not required to attend nor required to download/view past content. We are in various stages of organizing more webinars and virtual symposiums for the rest of this year.     Our last face to face seminar was on Feb 28, 2020 with a talk by John Lau, and our last symposium was Feb 20, 2020 — the Third Annual Heterogeneous Integration Roadmap (HIR) Symposium, with 170 attendees. Thankfully, no one was infected from attending either event.     Our membership is made up of a few hundred Bay Area members who are currently employed or have previously worked in high tech firms (and academia) in the area of device packaging. Those of us keeping the chapter active consist of a committee of officers who are voted in yearly. If interested, you can become an IEEE-EPS member by going to the EPS Website; also, we have many opportunities within the chapter for you to get involved — such as outreach programs to promote packaging interests to students and also to provide funding to underserved groups.

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Home  |  Contact IEEE Santa Clara Vally Chapter, EPS  |  Accessibility  |  Privacy & Opting Out of Cookies  |  Nondiscrimination Policy

IEEE Santa Clara Valley Chapter, EPS
Serving Silicon Valley and the SF Bay Area
© Copyright 2020 IEEE – All rights reserved. Use of this Web site signifies your agreement to the IEEE Terms and Conditions.
A not-for-profit organization, IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity.